A semiconductor element including a silicon carbide (SiC) semiconductor is attracting attention as a device that can achieve a high breakdown voltage and a low loss. As a structure thereof, a structure in which an epitaxial layer formed on a substrate having a low resistance (high doping concentration) acts as an operating layer is widely known. Particularly, in a semiconductor element (power device) for power, an epitaxial layer functions as a voltage sustaining layer (drift layer). Conventionally, a single layer structure has been generally used for the epitaxial layer (for example, Patent Document 1).
The epitaxial layer serving as a voltage sustaining layer of a power device ordinarily has a thickness of about 3 μm to 100 μm. However, depending on an operating voltage (the highest voltage assumed to be applied to the device; hereinafter also referred to as “assumed voltage”), the thickness may be set higher. In many cases, a doping concentration of an impurity (dopant) in the epitaxial layer is at most on the order of about 1016/cm3. However, depending on the operating voltage, it may be set on or below the order of 1015/cm3.
On the other hand, in a low resistance crystal that is a substrate, a dopant is often doped at a high concentration of 1019/cm3 or therearound. Therefore, the doping concentrations in the substrate and in the epitaxial layer are largely different. Since the doping concentration influences a crystal lattice constant, the lattice constants of the substrate and the epitaxial layer are largely different. This difference in the lattice constant (lattice mismatch) is a factor that causes a crystal defect, and thus deteriorates the crystal quality of the epitaxial layer particularly when the epitaxial layer has a large thickness. Deterioration in the crystal quality of the epitaxial layer causes a problem that the mobility of carriers decreases and an element resistance increases.
One known method for solving this problem adopts a technique in which a buffer layer having an intermediate doping concentration is interposed between a substrate having a high doping concentration and an epitaxial layer having a low doping concentration. For example, Patent Document 2 discloses that a buffer layer having a doping concentration of 2×1015 to 3×1019/cm3 and a thickness of 0.3 to 15 μm is provided to (11-20)-plane SiC crystal. Patent Document 2 also discloses, as a structure of the buffer layer, a single layer structure having a uniform doping concentration, a stepwise graded structure in which the doping concentration is varied stepwise in the thickness direction of the buffer layer, and a continuous graded structure in which the doping concentration is varied continuously in the thickness direction of the buffer layer.
Patent Document 3 discloses a buffer layer that is provided to a (0001)-plane or (000-1)-plane SiC crystal. In an example shown in Patent Document 3, for the purpose of suppressing introduction of basal plane dislocation into an epitaxial layer, the doping concentration of the buffer layer is set to be 1/10 to ½ of the doping concentration of a base layer, and a distribution of such a doping concentration has a stepwise graded structure.
Moreover, Patent Document 4 discloses a technique in which a high doping concentration layer is formed in a part of a drift layer in order to suppress an influence of a defect contained in a substrate given to the drift layer. Patent Document 5 shows a technique in which, in a drift layer of a field effect transistor, a high doping concentration layer is formed in a portion serving as a channel region and in a portion located at the n region side of the pn junction.